RF passive circuit and RF amplifier with via-holes

ABSTRACT

An input matching parallel inductor  114  which utilizes a spiral inductor, and an input matching parallel capacitor  115  which utilizes an MIM capacitor, both being constituting elements of an input matching circuit portion  125 , form an input matching parallel capacitor  115  inside an input matching circuit via-hole  121  being formed by applying a method of surface via-hole to the front surface of a GaAs substrate  124 . A choke inductor  119  which utilizes a spiral inductor, and a bypass capacitor  120  which utilizes an MIM capacitor, both being constituting elements of a drain voltage feeding circuit  107 , form a bypass capacitor  120  inside a drain voltage feeding circuit via-hole  123  formed by applying a method of surface via-hole to the front surface of the GaAs substrate  124 . A drain voltage terminal  136  is extended by a drawing wire  135  from between the spiral inductor and the drain voltage feeding circuit via-hole  123.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

This invention relates to a technology for making smaller and lighter RFpassive circuits and RF amplifiers equipped with via-holes.

(2) Prior Art

Recently, various types of mobile communication tools, such as portablephones or portable information terminals have been commercialized allover the world. As portable phones, cellular phones for bands of 900 MHzand 1.5 GHz, and Personal Handyphone System (PHS) for a band of 1.9 GHzare two examples that are commercialized in Japanese market. Otherexamples include world-famous GSM, and CDMA among the technologiesadopted in PCS (Personal Communications Services) in the U.S.A.

As a third-generation mode following the analogue mode and the digitalmode, IMT2000 is planned to be commercialized in the future.

In developing mobile communication terminals especially portableterminals, it is an inevitable trend to seek smaller and lighterterminals. Accordingly, it is important to achieve a technology formaking smaller and lighter components for these terminals.

As a trend, it is desired to make high frequency components of theportable terminals as a monolithic microwave IC (MMIC). The MMIC, inwhich active elements, their matching circuits, and bias circuits areintegrated on the same substrate, is more advantageous in making smallerproducts than a Hybrid IC which is structured to have circuits and biaselectricity-feeding circuits as outside-chips.

Even using the MMIC, it is required to ground circuit elements.Conventional grounding methods include a method of wire-bonding from thesurface of semiconductor substrates, and a via-hole method. It is moreeffective to use the via-hole method in achieving high-quality and lowcost for packaging, which makes the via-hole method more frequentlyadopted in the MMIC.

The following is a description of an example of a conventional type ofRF passive circuit and RF amplifier equipped with via-holes withreference to FIGS. 8A-8D.

FIG. 8A is a schematic circuit diagram of a conventional RF amplifierwhich includes RF passive circuits equipped with via-holes, and FIGS. 8Band 8C are pattern diagrams of conventional RF passive circuits bothequipped with a via-hole.

As FIG. 8A shows, a source-ground type of RF amplifier is constructed byconnecting: a gate bias resistance 805 and an input matching circuit 806to a gate terminal 802; a drain voltage feeding circuit 807 and anoutput matching circuit 808 to a drain terminal 803; and a sourceterminal 804 to a ground terminal 809, in the field effective transistor(FET) 801. An input terminal 810 and an output terminal 811 are both 50Ω impedance, and the input matching circuit 806 and the output matchingcircuit 808 are adjusted to 50 Ω. Further, each of an input DC cutcapacitor 812 and an output DC cut capacitor 813 is inserted to theinput side and the output side respectively.

The input matching circuit 806 consists of an input matching parallelinductor 814, an input matching parallel capacitor 815, and an inputmatching serial inductor 816. The input matching parallel capacitor 815is grounded by an input matching circuit via-hole 821.

The output matching circuit 808 consists of an output matching serialinductor 817, and an output matching parallel capacitor 818. The outputmatching parallel capacitor 818 is grounded by an output matchingcircuit via-hole 822.

The drain voltage feeding circuit 807 consists of a choke inductor 819and a bypass capacitor 820. The bypass capacitor 820 is grounded by adrain voltage feeding circuit via-hole 823.

FIGS. 8B and 8C are both pattern diagrams of an RF passive circuit witha via-hole; each of them shows the input matching circuit 806 and thedrain voltage feeding circuit 807 respectively. FIG. 8D shows across-sectional view taken along line (A-A′) of FIG. 8B. The followingis a description of a common part between the input matching circuit 806and the drain voltage feeding circuit 807, taking an example of theinput matching circuit 806.

Constituting elements of the aforementioned input matching circuit 806is made, as a semiconductor substrate, on a surface of a GaAs substrate824. Both of the input matching parallel inductor 814 and the inputmatching serial inductor 816 are made in a spiral-electrode-pattern, andthe input matching parallel capacitor 815 is made in an MIM(Metal-Insulator-Metal) capacitor pattern.

As FIG. 8D shows, the spiral-electrode-pattern is made on the GaAssubstrate 824 which is covered by an insulator film 834 such as siliconoxide. Specifically, the spiral-electrode-pattern is a structure where alower wiring metal layer 831 which is made by gold/titanium vacuumevaporation is connected to an upper wiring metal layer 830 made bygold-plating by means of a contact hole 833, with a between-layerinsulator film 832 in between.

On the other hand, the MIM capacitor is a structure where an upperwiring metal 829 is formed on a dielectric layer 828 under which is anelectrode extended from the lower wiring metal layer 831; the upperwiring metal 829 is made by gold/titanium vacuum evaporation and thedielectric layer 828 is titanium oxide strontium (SrTiO3:STO) with apermittivity of 100 or more. The end of the electrode extended from theupper wiring metal 829 is connected to a ground metal layer 826 which issituated on the via-hole, as FIGS. 8B and 8C show.

The input matching circuit via-hole 821 can be formed by etching fromthe main surface of the GaAs substrate 824 where circuit elements weremade (a surface via-hole). Or, it could also be formed by etching fromthe other main surface (a backside via-hole). Inside the via-hole 821,an electric conducting film is conducted to a backside ground metal 829.This electric conducting film is electrically connected to the upperwiring metal 829 of the MIM capacitor through the ground metal layer826.

Further, as depicted in FIG. 8C, constituting elements of the drainvoltage feeding circuit 807 are formed, as a semiconductor substrate, onthe surface of the GaAs substrate 824. As for the choke inductor 819, aspiral-electrode-pattern is used, and as for the drain voltage feedingcircuit via-hole 823, either a surface via-hole or a backside via-holeis used for forming.

Note that a feeding terminal 825 is structured by extending a drainvoltage terminal 836 from the lower wiring metal layer 831 through anextending wire 835.

Thus structured as above, the following constituting elements of the RFpassive circuit are formed on and through the GaAs substrate: the spiralinductor, the MIM capacitor, and the via-hole. Moreover, as FIG. 8Cshows, the above three elements are positioned at a different locationtwo-dimentionally, and are connected to each other by wiring. Theelements constitute the RF amplifier with a help of the input matchingcircuit 808 and the drain voltage feeding circuit 807.

As seen above, the conventional type of RF amplifiers and RF passivecircuits cannot be made smaller in size, due to the two-dimensionalpositioning of the constituting elements of the drain voltage feedingcircuit 807, which inherently take much space.

SUMMARY OF THE INVENTION

Based on the stated problem, the object of the present invention is torealize smaller RF passive circuits and RF amplifiers equipped withvia-holes.

To achieve the above object, the present invention is characterized by astructure of being equipped with a spiral inductor formed on a mainsurface of a semiconductor substrate, and a via-hole made from the mainsurface and through the semiconductor substrate. The via-hole is made atthe position adjacent to the spiral inductor, with a dielectric layerand a wiring metal layer formed on a metal film of the via-hole so as tohold a capacity element between the metal film and the wiring metallayer, and the spiral inductor extends at one end to be electricallyconnected with the wiring metal layer.

The above structure enables to incorporate a capacitor in a via-hole,thereby enabling a three-dimensional location of the following threeelements on one semiconductor substrate; a spiral inductor, a capacitor,and a via-hole. Thus reduced occupancy will produce an effect ofenabling a smaller RF passive circuit and an RF amplifier made of the RFpassive circuits as main components.

Furthermore, the RF amplifier of the present invention is characterizedby a structure of utilizing the RF passive circuit equipped with thevia-hole as a matching circuit, or as an RF choke in a bias feedingcircuit.

Furthermore, an RF passive circuit of the present invention is equippedwith a spiral inductor formed on a main surface of a semiconductorsubstrate and a via-hole that is made from the main surface and goesthrough the semiconductor substrate. The via-hole is placed adjacent tothe spiral inductor, and on a metal film of the via-hole, a firstdielectric layer, a first wiring metal layer, a second dielectric layer,and a second wiring metal layer are formed in this order, so as to forma first capacity element between the metal film of the via-hole and thefirst wiring metal layer, and a second capacity element between thefirst wiring metal layer and the second wiring metal layer. The presentinvention is further structured to have the metal film and the secondwiring metal layer electrically connected so as to hold a staticcapacity determined by a sum of the first capacity element and thesecond capacity element. The present invention is further characterizedby a spiral inductor extending at one end to be electrically connectedto the first wiring metal layer.

This structure will help to make a smaller RF passive circuit and asmaller RF amplifier by enabling a three-dimensional location of aspiral inductor, a capacitor, and a via-hole. Moreover, a staticcapacity will be increased without increasing the occupancy, which willfacilitate designing of such a circuit as a bias feeding circuit of anRF amplifier which inherently requires large capacity.

In addition, the RF amplifier of the present invention is characterizedby utilizing the RF passive circuit equipped with a via-hole as amatching circuit, or as an RF choke of a bias feeding circuit.

Moreover, the RF passive circuit equipped with a via-hole ischaracterized by a metal film of the via-hole provided through a mainsurface of a semiconductor substrate which further extends along themain surface, and by a spiral metal layer formed on the extended part ofthe metal film, which works as an inductor with a dielectric layer inbetween. Here, the extended part of the metal film can be made in thesame spiral pattern as the spiral inductor which is formed on the metalfilm.

The above structure enables to accommodate a static capacity where theextended part of the metal layer and the spiral metal layer face eachother with a dielectric layer in between. This realizes athree-dimensional location of a spiral inductor, a capacitor, and avia-hole, thereby reducing the occupancy thereof. This also helps tomake a smaller RF passive circuit, and a smaller RF amplifier.

Moreover, the RF amplifier of the present invention is characterized byutilizing the RF passive circuit equipped with a via-hole as a matchingcircuit, or as an RF choke of a bias feeding circuit.

In addition, the RF passive circuit equipped with a via-hole that thepresent invention is applied to, is characterized by making a via-holethat goes through a semiconductor substrate, and by making a dielectriclayer so as to cover a metal film of the via-hole which is providedthrough a main surface of the semiconductor substrate, and by aninductor formed as a spiral metal layer which covers the dielectriclayer so as to face against the metal film at one part, where a capacityelement is held between the via-hole and the inductor.

The above structure enables a three dimensional location of a spiralinductor, a capacitor, and a via-hole from inside to the surface of thesemiconductor substrate, thereby reducing the occupancy thereof, andhelps to make a smaller RF passive circuit and a smaller RF amplifier.

In addition, the RF amplifier of the present invention is characterizedby utilizing an RF passive circuit equipped with a via-hole as amatching circuit, or as an RF choke of a bias feeding circuit.

Moreover, the RF passive circuit with a via-hole that the presentinvention is applied to, is characterized by being equipped with avia-hole that goes through a semiconductor substrate from the other mainsurface of the semiconductor substrate, and by having a dielectric layeron a metal film of a via-hole provided through the main surface of asemiconductor substrate, and having a metal layer on the dielectriclayer, and holding a capacity element between the metal film of thevia-hole and the metal layer.

The above structure realizes a three dimensional location of a capacitorand a via-hole on one semiconductor substrate, thereby reducing theoccupancy thereof. This realizes a smaller RF passive circuit and asmaller RF amplifier.

In addition, the RF amplifier of the present invention is characterizedby electrically connecting a wiring metal layer of the RF passivecircuit with a gate terminal of a common gate circuit of a FET, or witha base terminal of a common base circuit of a bipolar transistor, or byelectrically connecting, with a source terminal of a FET, a terminalwhich is a terminal of a resistance element electrically connected tothe metal layer, so as to form a self bias circuit.

In addition, the RF passive circuit of the present invention equippedwith a via-hole is characterized by making a via-hole that goes througha semiconductor substrate, and by forming a dielectric layer and awiring metal layer on a metal film of the via-hole, in this order, so asto hold a capacity element between a ground metal layer and the wiringmetal layer.

The above structure enables a three dimensional location of a capacitorand a via-hole on one semiconductor substrate, thereby reducing theoccupancy thereof. This helps making a smaller RF passive circuit and asmaller RF amplifier.

Moreover, the RF amplifier of the present invention is characterized byelectrically connecting a wiring metal layer of the RF passive circuitwith a gate terminal of a common gate circuit of a FET, or byelectrically connecting the wiring metal layer with a base terminal of acommon base circuit in a bipolar transistor, or by connecting a terminalof a resistance element of the RF passive circuit with the ground metallayer, and the other terminal to the wiring metal layer, so as to form aself bias circuit.

The RF passive circuit equipped with a via-hole that the presentinvention is applied to, is further characterized by making a via-holethat goes through a semiconductor substrate, and by forming, on a metalfilm of the via-hole, a first dielectric layer, a first wiring metallayer, a second dielectric layer, and a second wiring metal layer inthis order. The RF passive circuit of the present invention is furthercharacterized by having a first capacity element between the metal filmand the first wiring metal layer, and the second capacity elementbetween the first wiring metal layer and the second wiring metal layer,and by electrically connecting the metal film and the second wiringmetal layer, so as to form a static capacity determined by a sum of thefirst capacity element and the second capacity element.

The RF amplifier of the present invention is further characterized byelectrically connecting a first wiring metal layer of an RF passivecircuit equipped with a via-hole with a gate terminal of a common gatecircuit of a FET, or by electrically connecting a first wiring metallayer with a base terminal of a common base circuit of a bipolartransistor. Or the RF amplifier is characterized by electricallyconnecting one terminal of a resistance element with the metal film, andthe other terminal with the first wiring metal layer, and the terminalof the resistance element which is electrically connected with thesecond wiring metal layer is further electrically connected with asource terminal of the FET so as to form a self bias circuit.

DESCRIPTION OF THE DRAWINGS

These and other objects, advantages and features of the invention willbecome apparent from the following description thereof taken inconjunction with the accompanying drawings which illustrate a specificembodiment of the invention. In the drawings:

FIGS. 1A-1D show an RF passive circuit and an RF amplifier equipped withvia-holes according to the first embodiment of the present invention.FIG. 1A is a schematic circuit diagram that the RF passive circuit ofthe present invention is applied to. FIG. 1B is a plan view showing anelectrode pattern constituting a matching circuit which is one exampleof the RF passive circuit, and FIG. 1C is a plan view showing anelectrode pattern constituting a bias feeding circuit which is anotherexample of the RF passive circuit. Finally FIG. 1D is a cross-sectionalview of FIG. 1B.

FIGS. 2A-2D show an RF passive circuit and an RF amplifier equipped withvia-holes according to the second embodiment of the present invention.FIG. 2A is a schematic circuit diagram that the RF passive circuit ofthe present invention is applied to. FIG. 2B is a plan view showing anelectrode pattern constituting a matching circuit which is one exampleof the RF passive circuit, and FIG. 2C is a plan view showing anelectrode pattern constituting a bias feeding circuit which is anotherexample of the RF passive circuit. Finally FIG. 2D is a cross-sectionalview of FIG. 2B.

FIGS. 3A-3C show an RF passive circuit and an RF amplifier equipped withvia-holes according to the third embodiment of the present invention.FIG. 3A is a schematic circuit diagram that the RF passive circuit isapplied to. FIG. 3B is a plan view showing an electrode patternconstituting a matching circuit which is one example of the RF passivecircuit, and FIG. 3C is a cross-sectional view of FIG. 3B.

FIGS. 4A-4D show an RF passive circuit and an RF amplifier equipped withvia-holes according to the fourth embodiment of the present invention.FIG. 4A is a schematic circuit diagram that the RF passive circuit ofthe present invention is applied to. FIG. 4B is a plan view showing anelectrode pattern constituting a matching circuit which is one exampleof the RF passive circuit, and FIG. 4C is a plan view showing anelectrode pattern constituting a bias feeding circuit which is anotherexample of the RF passive circuit. Finally FIG. 4D is a cross-sectionalview of FIG. 4B.

FIGS. 5A-5D show an RF passive circuit and an RF amplifier equipped withvia-holes according to the fifth embodiment of the present invention.FIGS. 5A-5C are schematic circuit diagrams of the RF amplifierrespectively. FIG. 5D is a cross-sectional view of a passive circuitformed on a GaAs substrate which is applied to each circuit in FIGS.5A-5C.

FIGS. 6A-6C show an RF passive circuit and an RF amplifier equipped withvia-holes according to the sixth embodiment of the present invention.FIGS. 6A and 6B are schematic circuit diagrams of the RF amplifier, andFIG. 6C is a cross-sectional view of a passive circuit formed on a GaAssubstrate which is applied to each circuit in FIGS. 6A and 6B.

FIGS. 7A-7C show an RF passive circuit and an RF amplifier equipped withvia-holes according to the seventh embodiment of the present invention.FIGS. 7A and 7B are schematic circuit diagrams of the RF amplifier, andFIG. 7C is a cross-sectional view of a passive circuit formed on a GaAssubstrate which is applied to each circuit in FIGS. 7A and 7B.

FIGS. 8A-8D show a conventional type of RF passive circuit and RFamplifier equipped with via-holes. FIG. 8A is a schematic diagram. FIG.8B is a plan view showing a matching circuit formed on a substrate. FIG.8C is a plan view showing a bias feeding circuit formed on a substrate,and FIG. 8D is a cross-sectional view of FIG. 8C.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following is a description of RF passive circuits and RF amplifiersequipped with via-holes, which are the preferred embodiments of thepresent invention, with reference to the drawings.

1. First Embodiment

FIGS. 1A-1D are drawn to describe the first embodiment of the presentinvention.

FIG. 1A is a schematic circuit diagram of the RF amplifier and the RFpassive circuit that the present invention is applied to. The circuit isbasically the same as the one in FIG. 8A, with minor difference inreference numbers for parts and materials. Therefore description isomitted.

FIGS. 1B and 1C are both diagrams showing a plan view of structuresrealized by an input matching circuit portion 125 and a drain voltagefeeding circuit 107 in FIG. 1 (1), pertaining to the first embodiment.

FIG. 1B is a plan view of the input matching circuit portion 125. Aninput matching parallel inductor 114 is in a spiral-electrode-pattern,and an input matching parallel capacitor 115 is an MIM capacitor and iscreated inside an input matching circuit via-hole 121, which is asurface via-hole made from the front surface of the GaAs substrate 124.

The following is a detailed description of the above-mentioned structurewith reference to FIG. 1D, a cross-sectional diagram. The whole backsurface of the GaAs substrate 124 is covered by the back surface metallayer 127, and an insulator layer 134 is formed such as silicon oxide onan arbitrary part on the front surface of the GaAs substrate 124. On thefront surface of the GaAs substrate 124 where the insulator layer 134 isnot present, a via-hole 121 is formed by etching. On the insulator layer134, a lower wiring metal layer 131 made by gold-plating is formed in aspiral pattern, which is covered by a between-layer insulator film 132made of silicon nitride. This is then covered by an upper wiring metallayer 130 made by gold/titanium plating. As FIG. 1B shows, the upperwiring metal layer 130 is in a linear form. The upper wiring metal layer130 and the lower wiring metal layer 131 are connected to each other bya contact hole 133 going through the between-layer insulator film 132.Both metal layers, put together, constitute the input matching parallelinductor 114 equivalently.

The inside of the via-hole 121 is covered with a three-layer film madeof: a ground metal layer 126, a dielectric layer 128, a first wiringmetal layer for capacity element 129, from the bottom. The ground metallayer 126 contacts the back surface metal layer 127 on the bottom of thevia-hole and it extends along the edge of the via-hole on the frontsurface of the GaAs substrate. The dielectric layer 128 is made of suchmaterial as titanium oxide strontium (SrTiO3: STO) whose permittivity is100 or more. The first wiring metal layer for capacity element 129extends on the between-layer insulator film 132 so as to merge with theupper wiring metal layer 130. The three-layer film forms the inputmatching parallel capacitor 115, which has a static capacity determinedby the following elements: a permittivity of the dielectric layer 128,the space between the two metal layers 126 and 129, and the distancebetween the two layers.

The drain voltage feeding circuit 107 is structured basically the sameas the input matching circuit depicted in FIG. 1B. The only differenceis that a drain voltage terminal 136 is drawn from between a spiralinductor and a drain voltage feeding circuit via-hole 123 through adrawing wire 135. Further explanation is omitted accordingly.

The above structure, incorporating a capacitor into a via-hole, is moreadvantageous in making smaller terminals than conventional one thatpositions each element in different places.

Note that such devices as a bipolar trangister and a metal-oxidesemiconductor field-effect transistor (MOSFET) are to be alternativelyused as an active element of an RF amplifier.

Also note that although the description is confined to RF amplifiers,the present invention is applicable to other RF devices such as mixer,or VCO, too.

2. Second Embodiment

FIGS. 2A-2D are drawings depicted for the explanation of the secondembodiment of the present invention. The application circuits will notbe described since they are the same as those of FIG. 1A. FIG. 2Bdepicts an input matching circuit, and FIG. 2C depicts a drain voltagefeeding circuit. FIG. 2D is a cross-sectional view of both circuits.

The second embodiment has larger static capacity than the firstembodiment, realized by an input matching parallel capacitor 221 createdinside a via-hole 215. That is, the second embodiment has a five-layerfilm inside the via-hole 215 made by stacking: a ground metal layer 226,a first dielectric layer 2281, a first wiring metal layer for capacityelement 2291, a second dielectric layer 2282, and a second wiring metallayer for capacity element 2292, from the bottom. Note that the threemetal layers are made of the same metal material, which is the samematerial used in the first embodiment. Likewise, all the two dielectriclayers, in this second embodiment, are made of the same dielectricmaterial, which is the same material as the first embodiment. The fivelayers are connected in some parts; the first dielectric layer 2281 andthe second dielectric layer 2282 are connected at one end of both layersabove the GaAs substrate, over which the ground metal layer 226 and thesecond wiring metal layer for capacity element 2292 are connected.

This structure enables nearly twice as much space as the firstembodiment where the metal layers face each other, since both the groundmetal layer 226 and the second wiring metal layer for capacity element2292 are structured to face against the first wiring metal layer forcapacity element 2291. Therefore, if the permittivity of the dielectriclayer is the same, the static capacity will be nearly twice as large asthe first embodiment. Moreover, it does not damage the advantage inmaking smaller terminals since the total occupancy stays the same as thefirst embodiment.

3. Third Embodiment

FIGS. 3A-3C are depicted for the explanation of the third embodiment.

FIG. 3A is a plan view showing a schematic circuit diagram for an RFamplifier the third embodiment is applied to. The circuits are the sameas those depicted in FIG. 8A, whose description is omitted accordingly.

FIG. 3B shows a plan view of an input matching circuit portion 325 and adrain voltage feeding circuit 307, both as parts of an RF amplifier ofthe third embodiment. FIG. 3C is a cross-sectional view of FIG. 3B.

The following focuses on the input matching circuit portion 325 fordetailed description.

First, a first wiring metal layer 330 is formed by gold/titanium vacuumevaporation in a spiral pattern seen from the above; it is formed so asto cover an insulator film 334 made of such materials as silicon oxideon a GaAs substrate 324. Next, a dielectric layer 328 made of titaniumoxide strontium which has a permittivity of 100 or more is applied onthe first wiring metal layer 330, in just about the same form as thefirst wiring metal layer 330, seen from the above. Then, the dielectriclayer 328, in turn, is covered by a second wiring metal layer 331 madeby gold-plating or gold/titanium vacuum evaporation, also in just aboutthe same form as the rest. The center of the spiral of the first wiringmetal layer 330 is connected, at the end, to a ground metal layer 326above the via-hole, and is grounded by the ground metal layer 326 andthe via-hole.

The third embodiment enables to have an input matching parallelcapacitor 315 since the first wiring metal layer 330 is structured toface the second wiring metal layer 331 with the dielectric layer 328 inbetween. Moreover with this embodiment, the second wiring metal layer331 is structured also to work as an inductor against high frequencies,as formed spirally and lengthy. Accordingly, the structure of FIGS. 3Band 3C, by grounding the capacitor at one end and connecting to aninductor at the other end, enables the input matching circuit portion325 and the drain voltage feeding circuit 307 equivalently.

4. Fourth Embodiment

FIGS. 4A-4D are drawn to describe the fourth embodiment of the presentinvention.

FIG. 4A is a schematic circuit diagram for an RF passive circuit and anRF amplifier that this embodiment is applied to. The circuit in FIG. 4Ais the same as FIG. 8A as self-explanatory, which does not probably needfurther explanation.

FIGS. 4B and 4C are plan views showing an input matching circuit portion425 and a drain voltage feeding circuit 407 respectively, both showingtheir circuit patterns, and FIG. 4D is a cross-sectional diagramthereof. The following description is confined to the input matchingcircuit portion, since it has many parts in common with the drainvoltage feeding circuit 407.

An input matching circuit via-hole 421 is placed underneath the centerof the spiral of an input matching parallel inductor 414.

The input matching circuit via-hole 421 is made using a backsidevia-hole method from the back of the GaAs substrate 424. The groundmetal layer 426, made by gold-plating or gold/titanium vacuumevaporation, is on the via-hole 421 and is conducted to the backsideground metal layer 427.

On the ground metal layer 426, a dielectric layer 428 made of titaniumoxide strontium (SrTiO3:STO) with a permittivity of 100 or more isformed, which has approximately the same form as the ground metal layer426 seen from the above. On this dielectric layer 428, in turn, a lowerwiring metal 429 is formed by gold/titanium vacuum evaporation. An MIMcapacitor formed by the ground metal layer 426, the dielectric layer428, and the lower wiring metal 429 put together, makes an inputmatching parallel capacitor 415.

Around the MIM capacitor and on the GaAs substrate 424, a between-layerinsulator film 432 and an insulator film 434 made of silicon oxide forexample are formed, which are then covered by an upper wire 430 in aspiral pattern made by such method as gold/titanium vacuum evaporationmethod. The center of the upper wire 430 is conducted to the lowerwiring metal 429 via a contact hole 433. The upper wire 430 and thelower wiring metal 429 form a spiral-formed inductor.

The fourth embodiment, just as the third embodiment, grounds one end ofthe capacitor, while connecting the other end to the inductor, whichforms equivalently the input matching circuit portion 425 depicted inFIG. 4A.

5. Fifth Embodiment

FIGS. 5A-5D are drawn to describe the fifth embodiment of the presentinvention.

FIG. 5A shows a schematic circuit diagram of an RF amplifier that thefifth embodiment is applied to.

The RF amplifier depicted in FIG. 5A uses a common gate type FET. Abypass capacitor 536 and a gate voltage terminal 537 are connected to agate terminal 502 of a FET 501; the bypass capacitor 536 is grounded bya ground via-hole 539. An input matching circuit 506 and a chokeinductor 540 are connected to a source terminal 504, and at the terminalof the choke inductor 540, a source voltage terminal 538 is connected. Adrain terminal 503 is connected to an output matching circuit 508, achoke inductor 519, and a bypass capacitor 520. An input terminal 510and an output terminal 511 are both 50 Ω impedance, and the inputmatching circuit 506 and the output matching circuit 508 are adjusted to50 Ω.

The structures described in the first, second, third, and fourthembodiments, are applicable to the input matching circuit 506 and theoutput matching circuit 508.

FIG. 5B is a schematic circuit diagram showing an RF amplifier using acommon base type bipolar transistor. A bypass capacitor 536 and a basevoltage terminal 543 are connected to a base terminal 542 of a bipolartransistor 541. The bypass capacitor 536 is grounded by the groundvia-hole 539. An input matching circuit 506 and a choke inductor 540 areconnected to an emitter terminal 544. At the terminal of the chokeinductor 540, an emitter voltage terminal 545 is connected. Finally anoutput matching circuit 508, a choke inductor 519, and a bypasscapacitor 520 are connected to a collector terminal 546. Both of aninput terminal 510 and an output terminal 511 are 50 Ω impedance, andboth of the input matching circuit 506 and the output matching terminal508 are adjusted to 50 Ω.

The structures described in the first, second, third, and fourthembodiments are applicable to the input matching circuit 506 and theoutput matching circuit 508.

FIG. 5C is a schematic circuit diagram showing an RF amplifier using asource ground type FET which uses a self-bias method. A gate biasresistance 505 and an input matching circuit 506 are connected to a gateterminal 502 of a FET 501. A self bias resistance 547 and a self biasbypass capacitor 548 are connected to a source terminal 504, which isgrounded by a ground via-hole 538. Finally an output matching circuit508 a choke inductor 519, and a bypass capacitor 520 are connected to adrain terminal 503. An input terminal 510 and an output terminal 511 areboth 50 Ω0 impedance, and the input matching circuit 506 and the outputmatching circuit 508 are adjusted to 50 Ω.

The structures described in the first, second, third, and fourthembodiment are applicable to the input matching circuit 506 and theoutput matching circuit 508.

FIG. 5D is a cross-sectional view of a circuit pattern constituting acapacitor grounded by a via-hole at one end.

The ground via-hole 539 depicted in FIGS. 5A-5C is made by a backsidevia-hole method from the back of the GaAs substrate 524. The groundmetal layer 526, made by gold-plating or gold/titanium vacuumevaporation, is conducted to the backside ground metal layer 527 of theGaAs substrate 524.

A dielectric layer 528 which is made of titanium oxide strontium(SrTiO3:STO) with a permittivity of 100 or more is formed on the groundmetal layer 526. On this dielectric layer 528, a wiring metal 529 isformed by such method as gold/titanium vacuum evaporation. A bypasscapacitor 536 and a self bias bypass capacitor 548 are formed using aMIM capacitor, which is obtained by combining the ground metal layer526, the dielectric layer 528, and the wiring metal 529.

The circuit structure depicted in FIGS. 5A and 5B is obtained byelectrically connecting the wiring metal 529 and the gate terminal 502.

Furthermore, the circuit structure in FIG. 5C is obtained byelectrically connecting one end of the self bias resistance 547 to thewiring metal 529, and the other end to the ground metal layer 526. Or,the circuit structure is alternatively obtained by using the insulatorlayer 534 formed around the dielectric layer 528 as a resistance layer,substituting it for the self bias resistance 547.

The fifth embodiment is structured to enable to make smaller terminalsby placing the via-hole and the capacitor in the same position on thesubstrate.

6. Sixth Embodiment

FIGS. 6A-6C are drawn to explain the sixth embodiment.

FIG. 6A shows an RF amplifier that the sixth embodiment is applied to.

FIGS. 6A and 6B are the same as FIGS. 5A and 5B respectively.Explanation of the circuit pertaining FIGS. 6A and 6B is omittedaccordingly.

The circuit described in the first, second, third, and fourthembodiments of the present invention (i.e. FIGS. 1A, 2A, 3A, and 4A) isapplicable to an input matching circuit 606 and an output matchingcircuit 608.

A ground via-hole 638 depicted in FIGS. 6A-6C is formed by a surfacevia-hole method from the front surface of a GaAs substrate 624. Insidethe ground via-hole 638, a bypass capacitor 636 and a self bias bypasscapacitor 648 are formed. A ground metal layer 626 is formed, bygold-plating or gold/titanium vacuum evaporation, both inside and aroundthe via-hole on the GaAs substrate 624. The ground metal layer 626 isconducted to a backside ground metal layer 627 on the GaAs substrate624. A dielectric layer 628 made of titanium oxide strontium(SrTiO3:STO) which has a permittivity of 100 or more is formed on theground metal layer 626. On the dielectric layer 628, in turn, a firstwiring metal layer for capacity element 629 is formed by such method asa gold/titanium vacuum evaporation method. From the above, a bypasscapacitor 636 and a self bias bypass capacitor 648 are formed ascapacitor elements, by the ground metal layer 626, the first wiringmetal layer for capacity element 629, and the dielectric layer 628.

7. Seventh Embodiment

FIGS. 7A-7C show the seventh embodiment of the present invention, whichhas a larger capacitor than the sixth embodiment.

The seventh embodiment is mostly the same as the sixth embodiment excepthow the capacitor is structured. The following description focuses onthis point accordingly.

As FIG. 7C shows, a ground via-hole 738 is made from the front surfaceof a GaAs substrate 724 using a surface via-hole method, so as to form abypass capacitor inside. A ground metal layer 726 is made inside theground via-hole 738 and also around the upper part thereof bygold-plating or gold/titanium vacuum evaporation. The ground metal layeris conducted to a backside ground metal layer 727. On the ground metallayer 726, a first dielectric layer 7281 is formed which is made oftitanium oxide strontium (SrTiO3:STO) with a permittivity of 100 ormore. Then, on this first dielectric layer 7281, a first wiring metallayer for capacity element 7291 is made by such method as gold/titaniumvacuum evaporation.

Further, on the first wiring metal layer for capacity element 7291, asecond dielectric layer 7282 is formed made of titanium oxide strontium(SrTiO3:STO) with a permittivity of 100 or more, which is in turncovered by a second wiring metal layer for capacity element 7292 made bysuch method as gold/titanium vacuum evaporation. Note that the groundmetal layer 726 and the second wiring metal layer for capacity element7292 are electrically connected.

The seventh embodiment is thus structured to create two capacityelements; the first capacity element by means of the ground metal layer726, the first wiring metal layer for capacity element 7291, and thefirst dielectric layer 7281; and the second capacity element by means ofthe first wiring metal layer for capacity element 7291, the secondwiring metal layer for capacity element 7292, and the second dielectriclayer 7282. From equivalent circuit point of view, a bypass capacitor iscreated by connecting the first capacity element and the second capacityelement in parallel (i.e. the capacity being a sum of the first and thesecond capacity elements).

Although the present invention has been fully described by way ofexamples with reference to the accompanying drawings, it is to be notedthat various changes and modifications will be apparent to those skilledin the art.

Therefore, unless such changes and modifications depart from the scopeof the present invention, they should be construed as being includedtherein.

1. An RF passive circuit comprising: a semiconductor substrate; a spiralinductor which is formed on a main surface of the semiconductorsubstrate; a via-hole which is formed at a position adjacent to thespiral inductor by applying a metal film on an inside wall of a holeprovided through the semiconductor substrate; a dielectric layer whichis formed on the metal film; and a wiring metal layer which is formed onthe dielectric layer and holds a capacitor between the via-hole; whereinone end of the spiral inductor extends to be connected with the wiringmetal layer.
 2. The RF passive circuit of claim 1, wherein the spiralinductor has a double layer structure having an upper wiring metal layerand a lower wiring metal layer, where at least one of the wiring metallayers is in a spiral pattern, and where the wiring metal layers areconnected to each other, with a contact hole therebetween.
 3. An RFchoke used in at least one of a matching circuit and a bias feedingcircuit, both circuits being included in an RF amplifier, the RF chokecomprising: a semiconductor substrate where at least one of the matchingcircuit and the bias feeding is circuit incorporated; a spiral inductorwhich is formed on a main surface of the semiconductor substrate; avia-hole which is formed at a position adjacent to the spiral inductorby applying a metal film on an inside wall of a hole provided throughthe semiconductor substrate; a dielectric layer which is formed on themetal film; and a wiring metal layer which is formed on the dielectriclayer and holds a capacitor between the via-hole, wherein one end of thespiral inductor extends to be connected with the wiring metal layer.4.-6. (canceled)
 7. An RF passive circuit comprising: a semiconductorsubstrate; a via-hole which is formed by applying a metal film on aninside wall of a hole provided through the semiconductor substrate; awiring metal layer which is formed on a main surface of thesemiconductor substrate and is electrically connected to the via-hole;and an inductor which is made of a metal film in a spiral pattern and isformed on the first wiring metal layer with a dielectric layertherebetween.
 8. The RF passive circuit of claim 7, wherein the wiringmetal layer is in the same parallel pattern as the inductor.
 9. An RFchoke used in at least one of a matching circuit and a bias feedingcircuit, both circuits being included in an RF amplifier, the RF chokecomprising: a semiconductor substrate where at least one of the matchingcircuit and the bias feeding circuit is incorporated; a via-hole whichis formed by applying a metal film on an inside wall of a hole providedthrough the semiconductor substrate; a wiring metal layer which isformed on a main surface of the semiconductor substrate and iselectrically connected to the via-hole; and an inductor which is made ofa metal film in a spiral pattern and is formed on the first wiring metallayer with a dielectric layer therebetween. 10.-11. (canceled)
 12. An RFpassive circuit comprising: a semiconductor substrate; a dielectriclayer which is formed on a first main surface of the semiconductorsubstrate; a via-hole which is formed by applying a metal film on aninside wall of a hole provided through a second main surface of thesemiconductor substrate until the hole reaches the dielectric layer; anda metal layer formed on the dielectric layer which holds a staticcapacity between the metal film of the via-hole and the metal layer. 13.The RF passive circuit of claim 12, further comprising: a resistanceelement whose one terminal is electrically connected to the metal layer,and the other terminal to the via-hole.
 14. An RF amplifier comprising:a semiconductor substrate; a dielectric layer which is formed on a firstmain surface of the semiconductor substrate; a via-hole which is formedby applying a metal film on an inside wall of a hole provided through asecond main surface of the semiconductor substrate until the holereaches the dielectric layer; a metal layer formed on the dielectriclayer which holds a static capacity between the metal film of thevia-hole and the metal layer; and a field effective transistor, mountedon the semiconductor substrate, which has a common gate circuit having agate terminal electrically connected to the metal layer.
 15. An RFamplifier comprising: a semiconductor substrate; a dielectric layerwhich is formed on a first main surface of the semiconductor substrate;a via-hole which is formed by applying a metal film on an inside wall ofa hole provided through a second main surface of the semiconductorsubstrate until the hole reaches the dielectric layer; a metal layerformed on the dielectric layer which holds a static capacity between themetal film of the via-hole and the metal layer; and a bipolartransistor, mounted on the semiconductor substrate, which has a commonbase circuit having a base terminal electrically connected to the metallayer.
 16. An RF amplifier comprising: a semiconductor substrate; adielectric layer which is formed on a first main surface of thesemiconductor substrate; a via-hole which is formed by applying a metalfilm on an inside wall of a hole provided through a second main surfaceof the semiconductor substrate until the hole reaches the dielectriclayer; a metal layer formed on the dielectric layer which holds a staticcapacity between the metal film of the via-hole and the metal layer; aresistance element whose one terminal is electrically connected to thevia-hole and the other terminal to the metal layer; and a fieldeffective transistor mounted on the semiconductor substrate whose sourceterminal is connected to the other terminal of the resistance elementconnected to the metal layer, so as to form a self bias circuit.
 17. AnRF passive circuit comprising: a semiconductor substrate; a via-holewhich is formed by applying a metal film on an inside wall of a holeprovided through the semiconductor substrate; a dielectric layer whichis formed on an inside wall of the via-hole; and a wiring metal layerformed on the dielectric layer, which holds a static capacity betweenthe via-hole.
 18. The RF passive circuit of claim 17, furthercomprising: a resistance element whose one terminal is electricallyconnected to the metal film of the via-hole, and the other terminal tothe wiring metal layer.
 19. An RF amplifier comprising: a semiconductorsubstrate; a via-hole which is formed by applying a metal film on aninside wall of a hole provided through the semiconductor substrate; adielectric layer which is formed on an inside wall of the via-hole; awiring metal layer formed on the dielectric layer, which holds a staticcapacity between the via-hole; and a field effective transistor, mountedthe semiconductor substrate, which has a common gate circuit having agate terminal electrically connected to the wiring metal layer.
 20. AnRF amplifier comprising: a semiconductor substrate; a via-hole which isformed by applying a metal film on an inside wall of a hole providedthrough the semiconductor substrate; a dielectric layer which is formedon an inside wall of the via-hole; a wiring metal layer formed on thedielectric layer, which holds a static capacity between the via-hole;and a bipolar transistor, mounted on the semiconductor substrate, whichhas a common base circuit having a base terminal electrically connectedto the wiring metal layer.
 21. An RF amplifier comprising: asemiconductor substrate; a via-hole which is formed by applying a metalfilm on an inside wall of a hole provided through the semiconductorsubstrate; a dielectric layer which is formed on an inside wall of thevia-hole; a wiring metal layer formed on the dielectric layer, whichholds a static capacity between the via-hole; a resistance element whoseone terminal is electrically connected to the metal film of the via-holeand the other terminal to the metal layer; and a field effectivetransistor mounted the semiconductor substrate whose source terminal isconnected to the other terminal of the resistance element connected tothe metal layer, so as to form a self bias circuit.
 22. An RF passivecircuit comprising: a semiconductor substrate; a via-hole which isformed by applying a metal film on an inside wall of a hole providedthrough the semiconductor substrate; a first dielectric layer which isformed on an inside wall of the via-hole; a first wiring metal layerformed on the first dielectric layer which equivalently forms a firstcapacity element between the via-hole; a second dielectric layer whichis formed on the first wiring metal layer; and a second wiring metallayer formed on the second dielectric layer which equivalently forms asecond capacity element between the first wiring metal layer, whereinthe via-hole and the second wiring metal layer are electricallyconnected, and the sum of static capacity of the first capacity elementand the second capacity element are held between the via-hole and thefirst wiring metal layer.
 23. The RF passive circuit of claim 22,further comprising: a resistance element whose terminal is electricallyconnected either to the second wiring metal layer or to the via-hole,and the other terminal to the first wiring metal layer.
 24. An RFamplifier comprising: a semiconductor substrate; a via-hole which isformed by applying a metal film on an inside wall of a hole providedthrough the semiconductor substrate; a first dielectric layer which isformed on an inside wall of the via-hole; a first wiring metal layerformed on the first dielectric layer which equivalently forms a firstcapacity element between the via-hole; a second dielectric layer whichis formed on the first wiring metal layer; a second wiring metal layerformed on the second dielectric layer which equivalently forms a secondcapacity element between the first wiring metal layer, the via-hole andthe second wiring metal layer being electrically connected, and the sumof static capacity of the first capacity element and the second capacityelement being held between the via-hole and the first wiring metallayer; and a field effective transistor, mounted on the semiconductorsubstrate, which has a common gate circuit having a gate terminalelectrically connected to the first wiring metal layer.
 25. An RFamplifier comprising: a semiconductor substrate; a via-hole which isformed by applying a metal film on an inside wall of a hole through thesemiconductor substrate; a first dielectric layer which is formed on aninside wall of the via-hole; a first wiring metal layer formed on thefirst dielectric layer which equivalently forms a first capacity elementbetween the via-hole; a second dielectric layer which is formed on thefirst wiring metal layer; a second wiring metal layer formed on thesecond dielectric layer which equivalently forms a second capacityelement between the first wiring metal layer, the via-hole and thesecond wiring metal layer being electrically connected, and the sum ofstatic capacity of the first capacity element and the second capacityelement being held between the via-hole and the first wiring metallayer; and a bipolar transistor, mounted on the semiconductor substrate,which has a common base circuit having a base terminal electricallyconnected to the first wiring metal layer.
 26. An RF amplifiercomprising: a semiconductor substrate; a via-hole which is formed byapplying a metal film on an inside wall of a hole provided through thesemiconductor substrate; a first dielectric layer which is formed on aninside wall of the via-hole; a first wiring metal layer formed on thefirst dielectric layer which equivalently forms a first capacity elementbetween the via-hole; a second dielectric layer which is formed on thefirst wiring metal layer; a second wiring metal layer formed on thesecond dielectric layer which equivalently forms a second capacityelement between the first wiring metal layer, the via-hole and thesecond wiring metal layer being electrically connected, and the sum ofstatic capacity of the first capacity element and the second capacityelement being held between the via-hole and the first wiring metallayer; a resistance element whose one terminal is electrically connectedeither to the second wiring metal layer or to the via-hole, and theother terminal to the first wiring metal layer; and a field effectivetransistor mounted on the semiconductor substrate whose source terminalis connected to the one terminal of the resistance element connectedeither to the second wiring metal layer or to the via-hole, so as toform a self bias circuit.